1From 32f07974c68c3f0bbd854f272e1447b0e6d63bfc Mon Sep 17 00:00:00 20012From: Chen Wang <unicorn_wang@outlook.com>3Date: Mon, 20 Oct 2025 11:33:43 +08004Subject: [PATCH 1/8] riscv: sophgo: dts: add PCIe controllers for SG204256Add PCIe controller nodes in DTS for Sophgo SG2042.7Default they are disabled.89Acked-by: Manivannan Sadhasivam <mani@kernel.org>10Signed-off-by: Han Gao <rabenda.cn@gmail.com>11Signed-off-by: Chen Wang <unicorn_wang@outlook.com>12Link: https://lore.kernel.org/r/b34d819cd763482e0ecbc5c5ea721f0101d1f844.1760929111.git.unicorn_wang@outlook.com13Signed-off-by: Inochi Amaoto <inochiama@gmail.com>14Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>15(cherry picked from commit 4e27aca4881ace1e9a812fc2c88b33dd84e29993)16---17 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++18 1 file changed, 88 insertions(+)1920diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi21index c5e49709b308..85d8b89cf9fc 10064422--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi23+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi24@@ -240,6 +240,94 @@ clkgen: clock-controller@7030012000 {25 #clock-cells = <1>;26 };2728+ pcie_rc0: pcie@7060000000 {29+ compatible = "sophgo,sg2042-pcie-host";30+ device_type = "pci";31+ reg = <0x70 0x60000000 0x0 0x00800000>,32+ <0x40 0x00000000 0x0 0x00001000>;33+ reg-names = "reg", "cfg";34+ linux,pci-domain = <0>;35+ #address-cells = <3>;36+ #size-cells = <2>;37+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,38+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,39+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,40+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,41+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;42+ bus-range = <0x0 0xff>;43+ vendor-id = <0x1f1c>;44+ device-id = <0x2042>;45+ cdns,no-bar-match-nbits = <48>;46+ msi-parent = <&msi>;47+ status = "disabled";48+ };49+50+ pcie_rc1: pcie@7060800000 {51+ compatible = "sophgo,sg2042-pcie-host";52+ device_type = "pci";53+ reg = <0x70 0x60800000 0x0 0x00800000>,54+ <0x44 0x00000000 0x0 0x00001000>;55+ reg-names = "reg", "cfg";56+ linux,pci-domain = <1>;57+ #address-cells = <3>;58+ #size-cells = <2>;59+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,60+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,61+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,62+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,63+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;64+ bus-range = <0x0 0xff>;65+ vendor-id = <0x1f1c>;66+ device-id = <0x2042>;67+ cdns,no-bar-match-nbits = <48>;68+ msi-parent = <&msi>;69+ status = "disabled";70+ };71+72+ pcie_rc2: pcie@7062000000 {73+ compatible = "sophgo,sg2042-pcie-host";74+ device_type = "pci";75+ reg = <0x70 0x62000000 0x0 0x00800000>,76+ <0x48 0x00000000 0x0 0x00001000>;77+ reg-names = "reg", "cfg";78+ linux,pci-domain = <2>;79+ #address-cells = <3>;80+ #size-cells = <2>;81+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,82+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,83+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,84+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,85+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;86+ bus-range = <0x0 0xff>;87+ vendor-id = <0x1f1c>;88+ device-id = <0x2042>;89+ cdns,no-bar-match-nbits = <48>;90+ msi-parent = <&msi>;91+ status = "disabled";92+ };93+94+ pcie_rc3: pcie@7062800000 {95+ compatible = "sophgo,sg2042-pcie-host";96+ device_type = "pci";97+ reg = <0x70 0x62800000 0x0 0x00800000>,98+ <0x4c 0x00000000 0x0 0x00001000>;99+ reg-names = "reg", "cfg";100+ linux,pci-domain = <3>;101+ #address-cells = <3>;102+ #size-cells = <2>;103+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,104+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,105+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,106+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,107+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;108+ bus-range = <0x0 0xff>;109+ vendor-id = <0x1f1c>;110+ device-id = <0x2042>;111+ cdns,no-bar-match-nbits = <48>;112+ msi-parent = <&msi>;113+ status = "disabled";114+ };115+116 clint_mswi: interrupt-controller@7094000000 {117 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";118 reg = <0x00000070 0x94000000 0x00000000 0x00004000>;119--1202.52.0121122123From 3ae935bd5d3c18f8f7136b1cee5ed0a5ca058cc0 Mon Sep 17 00:00:00 2001124From: Chen Wang <unicorn_wang@outlook.com>125Date: Mon, 20 Oct 2025 11:34:05 +0800126Subject: [PATCH 2/8] riscv: sophgo: dts: enable PCIe for PioneerBox127128Enable PCIe controllers for PioneerBox, which uses SG2042 SoC.129130Signed-off-by: Chen Wang <unicorn_wang@outlook.com>131Link: https://lore.kernel.org/r/ec474c5eefb79626dd6a4d65454da9109aaf2f4d.1760929111.git.unicorn_wang@outlook.com132Signed-off-by: Inochi Amaoto <inochiama@gmail.com>133Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>134(cherry picked from commit b85ad0d06a19de95d41f91162389a1bbb461a405)135---136 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++137 1 file changed, 12 insertions(+)138139diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts140index ef3a602172b1..c4d5f8d7d4ad 100644141--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts142+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts143@@ -128,6 +128,18 @@ uart0-rx-pins {144 };145 };146147+&pcie_rc0 {148+ status = "okay";149+};150+151+&pcie_rc2 {152+ status = "okay";153+};154+155+&pcie_rc3 {156+ status = "okay";157+};158+159 &sd {160 pinctrl-0 = <&sd_cfg>;161 pinctrl-names = "default";162--1632.52.0164165166From 0a32b6d9573e423d8744283e0840ef6fedeaa8a6 Mon Sep 17 00:00:00 2001167From: Chen Wang <unicorn_wang@outlook.com>168Date: Mon, 20 Oct 2025 11:39:22 +0800169Subject: [PATCH 3/8] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X170171Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board,172which uses SG2042 SoC.173174Signed-off-by: Han Gao <rabenda.cn@gmail.com>175Signed-off-by: Chen Wang <unicorn_wang@outlook.com>176Link: https://lore.kernel.org/r/1ad96631cc9d9d7403a2bed5585d856fa101a2ef.1760929111.git.unicorn_wang@outlook.com177Tested-by: Han Gao <rabenda.cn@gmail.com>178Signed-off-by: Inochi Amaoto <inochiama@gmail.com>179Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>180(cherry picked from commit c6c215099e89b1eb71ed6592163ae5b530f4538e)181---182 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++++++++++++183 1 file changed, 12 insertions(+)184185diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts186index 3320bc1dd2c6..a186d036cf36 100644187--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts188+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts189@@ -164,6 +164,18 @@ phy0: phy@0 {190 };191 };192193+&pcie_rc0 {194+ status = "okay";195+};196+197+&pcie_rc1 {198+ status = "okay";199+};200+201+&pcie_rc2 {202+ status = "okay";203+};204+205 &pinctrl {206 emmc_cfg: sdhci-emmc-cfg {207 sdhci-emmc-wp-pins {208--2092.52.0210211212From ede4438fe8863d66b65e09c75327ccd793318344 Mon Sep 17 00:00:00 2001213From: Chen Wang <unicorn_wang@outlook.com>214Date: Mon, 20 Oct 2025 11:40:09 +0800215Subject: [PATCH 4/8] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0216217Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board,218which uses SG2042 SoC.219220Signed-off-by: Han Gao <rabenda.cn@gmail.com>221Signed-off-by: Chen Wang <unicorn_wang@outlook.com>222Link: https://lore.kernel.org/r/50a753f9b8cbd5a90b5b2df737f87fc77a9b33a7.1760929111.git.unicorn_wang@outlook.com223Tested-by: Han Gao <rabenda.cn@gmail.com>224Signed-off-by: Inochi Amaoto <inochiama@gmail.com>225Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>226(cherry picked from commit 579d6526aa43a155c8685a88ef8350a8c29afa47)227---228 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++229 1 file changed, 12 insertions(+)230231diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts232index 46980e41b886..0cd0dc0f537c 100644233--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts234+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts235@@ -152,6 +152,18 @@ phy0: phy@0 {236 };237 };238239+&pcie_rc0 {240+ status = "okay";241+};242+243+&pcie_rc1 {244+ status = "okay";245+};246+247+&pcie_rc2 {248+ status = "okay";249+};250+251 &pinctrl {252 emmc_cfg: sdhci-emmc-cfg {253 sdhci-emmc-wp-pins {254--2552.52.0256257258From 1b39342a98604f24cb6c03f6a7eeed7389d3a5d1 Mon Sep 17 00:00:00 2001259From: Zixian Zeng <sycamoremoon376@gmail.com>260Date: Tue, 16 Sep 2025 21:22:50 +0800261Subject: [PATCH 5/8] riscv: dts: sophgo: Add SPI NOR node for SG2042262263Add SPI NOR controller node for SG2042264265Reviewed-by: Chen Wang <unicorn_wang@outlook.com>266Tested-by: Chen Wang <unicorn_wang@outlook.com>267Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>268Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-1-b5d9024fe1c8@gmail.com269Signed-off-by: Inochi Amaoto <inochiama@gmail.com>270Signed-off-by: Chen Wang <unicorn_wang@outlook.com>271Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>272(cherry picked from commit 59dc89fdfe0bbcce186116651bd017cfb9f70fc0)273---274 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 ++++++++++++++++++++++++275 1 file changed, 24 insertions(+)276277diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi278index 85d8b89cf9fc..ec99da39150f 100644279--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi280+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi281@@ -68,6 +68,30 @@ soc: soc {282 interrupt-parent = <&intc>;283 ranges;284285+ spifmc0: spi@7000180000 {286+ compatible = "sophgo,sg2042-spifmc-nor";287+ reg = <0x70 0x00180000 0x0 0x1000000>;288+ #address-cells = <1>;289+ #size-cells = <0>;290+ clocks = <&clkgen GATE_CLK_AHB_SF>;291+ interrupt-parent = <&intc>;292+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;293+ resets = <&rstgen RST_SF0>;294+ status = "disabled";295+ };296+297+ spifmc1: spi@7002180000 {298+ compatible = "sophgo,sg2042-spifmc-nor";299+ reg = <0x70 0x02180000 0x0 0x1000000>;300+ #address-cells = <1>;301+ #size-cells = <0>;302+ clocks = <&clkgen GATE_CLK_AHB_SF>;303+ interrupt-parent = <&intc>;304+ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;305+ resets = <&rstgen RST_SF1>;306+ status = "disabled";307+ };308+309 i2c0: i2c@7030005000 {310 compatible = "snps,designware-i2c";311 reg = <0x70 0x30005000 0x0 0x1000>;312--3132.52.0314315316From 99aa0f0d6d4c80fb9db6bfb43af35bfa15852eae Mon Sep 17 00:00:00 2001317From: Zixian Zeng <sycamoremoon376@gmail.com>318Date: Tue, 16 Sep 2025 21:22:51 +0800319Subject: [PATCH 6/8] riscv: dts: sophgo: Enable SPI NOR node for PioneerBox320321Enable SPI NOR node for PioneerBox device tree322323According to PioneerBox schematic, SPI-NOR Flash cannot support QSPI324due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.325326Reviewed-by: Chen Wang <unicorn_wang@outlook.com>327Tested-by: Chen Wang <unicorn_wang@outlook.com>328Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>329Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-2-b5d9024fe1c8@gmail.com330Signed-off-by: Inochi Amaoto <inochiama@gmail.com>331Signed-off-by: Chen Wang <unicorn_wang@outlook.com>332Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>333(cherry picked from commit f49314cbbc98f9ab2bf4eb82ccacbf79f179db6c)334---335 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 24 +++++++++++++++++++336 1 file changed, 24 insertions(+)337338diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts339index c4d5f8d7d4ad..54d8386bf9c0 100644340--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts341+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts342@@ -150,6 +150,30 @@ &sd {343 status = "okay";344 };345346+&spifmc0 {347+ status = "okay";348+349+ flash@0 {350+ compatible = "jedec,spi-nor";351+ reg = <0>;352+ spi-max-frequency = <50000000>;353+ spi-tx-bus-width = <1>;354+ spi-rx-bus-width = <1>;355+ };356+};357+358+&spifmc1 {359+ status = "okay";360+361+ flash@0 {362+ compatible = "jedec,spi-nor";363+ reg = <0>;364+ spi-max-frequency = <50000000>;365+ spi-tx-bus-width = <1>;366+ spi-rx-bus-width = <1>;367+ };368+};369+370 &uart0 {371 pinctrl-0 = <&uart0_cfg>;372 pinctrl-names = "default";373--3742.52.0375376377From b15a729567e689dd17d61375f638181e31068831 Mon Sep 17 00:00:00 2001378From: Zixian Zeng <sycamoremoon376@gmail.com>379Date: Tue, 16 Sep 2025 21:22:52 +0800380Subject: [PATCH 7/8] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1381382Enable SPI NOR node for SG2042_EVB_V1 device tree383384According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI385due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.386387Signed-off-by: Han Gao <rabenda.cn@gmail.com>388Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>389Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-3-b5d9024fe1c8@gmail.com390Signed-off-by: Inochi Amaoto <inochiama@gmail.com>391Signed-off-by: Chen Wang <unicorn_wang@outlook.com>392Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>393(cherry picked from commit 11f4d84c9f724ec4c6810567d6b9713b054bb28b)394---395 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 24 ++++++++++++++++++++396 1 file changed, 24 insertions(+)397398diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts399index a186d036cf36..b116dfa904cd 100644400--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts401+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts402@@ -250,6 +250,30 @@ &sd {403 status = "okay";404 };405406+&spifmc0 {407+ status = "okay";408+409+ flash@0 {410+ compatible = "jedec,spi-nor";411+ reg = <0>;412+ spi-max-frequency = <50000000>;413+ spi-tx-bus-width = <1>;414+ spi-rx-bus-width = <1>;415+ };416+};417+418+&spifmc1 {419+ status = "okay";420+421+ flash@0 {422+ compatible = "jedec,spi-nor";423+ reg = <0>;424+ spi-max-frequency = <50000000>;425+ spi-tx-bus-width = <1>;426+ spi-rx-bus-width = <1>;427+ };428+};429+430 &uart0 {431 pinctrl-0 = <&uart0_cfg>;432 pinctrl-names = "default";433--4342.52.0435436437From 906690b188c3d0428cb8a0c0fb6f7900a7d0646d Mon Sep 17 00:00:00 2001438From: Zixian Zeng <sycamoremoon376@gmail.com>439Date: Tue, 16 Sep 2025 21:22:53 +0800440Subject: [PATCH 8/8] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2441442Enable SPI NOR node for SG2042_EVB_V2 device tree443444According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI445due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.446447Signed-off-by: Han Gao <rabenda.cn@gmail.com>448Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>449Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-4-b5d9024fe1c8@gmail.com450Signed-off-by: Inochi Amaoto <inochiama@gmail.com>451Signed-off-by: Chen Wang <unicorn_wang@outlook.com>452Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>453(cherry picked from commit af5eb17ff893bf6e52680a31059e1816749c2d20)454---455 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++456 1 file changed, 12 insertions(+)457458diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts459index 0cd0dc0f537c..b2ceae2d8829 100644460--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts461+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts462@@ -238,6 +238,18 @@ &sd {463 status = "okay";464 };465466+&spifmc1 {467+ status = "okay";468+469+ flash@0 {470+ compatible = "jedec,spi-nor";471+ reg = <0>;472+ spi-max-frequency = <50000000>;473+ spi-tx-bus-width = <1>;474+ spi-rx-bus-width = <1>;475+ };476+};477+478 &uart0 {479 pinctrl-0 = <&uart0_cfg>;480 pinctrl-names = "default";481--4822.52.0483